simulavr  1.1.0
atmega1284abase.cpp
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1  /*
2  ****************************************************************************
3  *
4  * simulavr - A simulator for the Atmel AVR family of microcontrollers.
5  * Copyright (C) 2001, 2002, 2003 Klaus Rudolph
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  ****************************************************************************
22  */
23 #include "atmega1284abase.h"
24 
25 #include "irqsystem.h"
26 #include "hwstack.h"
27 #include "hweeprom.h"
28 #include "hwwado.h"
29 #include "hwsreg.h"
30 #include "avrerror.h"
31 #include "avrfactory.h"
32 
37 
42 
47 
49  delete usart1;
50  delete usart0;
51  delete wado;
52  delete spi;
53  delete acomp;
54  delete ad;
55  delete aref;
56  delete admux;
57  delete gpior2_reg;
58  delete gpior1_reg;
59  delete gpior0_reg;
60  delete timer2;
61  delete timerIrq2;
62  delete timer1;
63  delete inputCapture1;
64  delete timerIrq1;
65  delete timer0;
66  delete timerIrq0;
67  delete extirqpc;
68  delete pcmsk3_reg;
69  delete pcmsk2_reg;
70  delete pcmsk1_reg;
71  delete pcmsk0_reg;
72  delete pcifr_reg;
73  delete pcicr_reg;
74  delete extirq012;
75  delete eifr_reg;
76  delete eimsk_reg;
77  delete eicra_reg;
78  delete rampz;
79  delete osccal_reg;
80  delete clkpr_reg;
81  delete stack;
82  delete eeprom;
83  delete irqSystem;
84  delete spmRegister;
85 }
86 
88  unsigned flash_bytes,
89  unsigned ee_bytes,
90  unsigned nrww_start):
91  AvrDevice(256-32, // I/O space size (above ALU registers)
92  ram_bytes, // RAM size
93  0, // External RAM size
94  flash_bytes), // Flash Size
95  porta(this, "A", true),
96  portb(this, "B", true),
97  portc(this, "C", true),
98  portd(this, "D", true),
99  gtccr_reg(&coreTraceGroup, "GTCCR"),
100  assr_reg(&coreTraceGroup, "ASSR"),
101  prescaler01(this, "01", &gtccr_reg, 0, 7),
102  prescaler2(this, "2", PinAtPort(&portb, 6), &assr_reg, 5, &gtccr_reg, 1, 7),
103  premux0(&prescaler01, PinAtPort(&portd, 4)),
104  premux1(&prescaler01, PinAtPort(&portd, 5)),
105  premux2(&prescaler2)
106 {
107  flagELPMInstructions = true;
108  fuses->SetFuseConfiguration(19, 0xff9962);
109  if(flash_bytes > 32U * 1024U) {
110  fuses->SetBootloaderConfig(nrww_start, (flash_bytes >> 1) - nrww_start, 9, 8);
111  spmRegister = new FlashProgramming(this, 128, nrww_start, FlashProgramming::SPM_MEGA_MODE);
112  } else {
113  fuses->SetBootloaderConfig(nrww_start, (flash_bytes >> 1) - nrww_start, 9, 8);
114  spmRegister = new FlashProgramming(this, 64, nrww_start, FlashProgramming::SPM_MEGA_MODE);
115  }
116 
117  irqSystem = new HWIrqSystem(this, 4, 31);
118 
119  eeprom = new HWEeprom(this, irqSystem, ee_bytes, 25, HWEeprom::DEVMODE_EXTENDED);
120  // initialize stack: size=11,12,13,15 bit and init to RAMEND
121  int stack_size;
122  if(ram_bytes > 2U * 1024U) {
123  if(ram_bytes > 4U * 1024U)
124  stack_size = 15;
125  else
126  stack_size = 13;
127  } else {
128  if(ram_bytes > 1U * 1024U)
129  stack_size = 11;
130  else
131  stack_size = 12;
132  }
133  stack = new HWStackSram(this, stack_size, true);
134  clkpr_reg = new CLKPRRegister(this, &coreTraceGroup);
136 
137  rampz = new AddressExtensionRegister(this, "RAMPZ", 1);
138 
139  eicra_reg = new IOSpecialReg(&coreTraceGroup, "EICRA");
140  eimsk_reg = new IOSpecialReg(&coreTraceGroup, "EIMSK");
141  eifr_reg = new IOSpecialReg(&coreTraceGroup, "EIFR");
143  extirq012->registerIrq(1, 0, new ExternalIRQSingle(eicra_reg, 0, 2, GetPin("D2")));
144  extirq012->registerIrq(2, 1, new ExternalIRQSingle(eicra_reg, 2, 2, GetPin("D3")));
145  extirq012->registerIrq(3, 2, new ExternalIRQSingle(eicra_reg, 4, 2, GetPin("B2")));
146 
147  pcicr_reg = new IOSpecialReg(&coreTraceGroup, "PCICR");
148  pcifr_reg = new IOSpecialReg(&coreTraceGroup, "PCIFR");
149  pcmsk0_reg = new IOSpecialReg(&coreTraceGroup, "PCMSK0");
150  pcmsk1_reg = new IOSpecialReg(&coreTraceGroup, "PCMSK1");
151  pcmsk2_reg = new IOSpecialReg(&coreTraceGroup, "PCMSK2");
152  pcmsk3_reg = new IOSpecialReg(&coreTraceGroup, "PCMSK3");
158 
159  timerIrq0 = new TimerIRQRegister(this, irqSystem, 0);
160  timerIrq0->registerLine(0, IRQLine("TOV0", 18));
161  timerIrq0->registerLine(1, IRQLine("OCF0A", 16));
162  timerIrq0->registerLine(2, IRQLine("OCF0B", 17));
163 
164  timer0 = new HWTimer8_2C(this,
165  &premux0,
166  0,
167  timerIrq0->getLine("TOV0"),
168  timerIrq0->getLine("OCF0A"),
169  PinAtPort(&portb, 3),
170  timerIrq0->getLine("OCF0B"),
171  PinAtPort(&portb, 4));
172 
173  timerIrq1 = new TimerIRQRegister(this, irqSystem, 1);
174  timerIrq1->registerLine(0, IRQLine("TOV1", 15));
175  timerIrq1->registerLine(1, IRQLine("OCF1A", 13));
176  timerIrq1->registerLine(2, IRQLine("OCF1B", 14));
177  timerIrq1->registerLine(5, IRQLine("ICF1", 12));
178 
180  timer1 = new HWTimer16_2C3(this,
181  &premux1,
182  1,
183  timerIrq1->getLine("TOV1"),
184  timerIrq1->getLine("OCF1A"),
185  PinAtPort(&portd, 5),
186  timerIrq1->getLine("OCF1B"),
187  PinAtPort(&portd, 4),
188  timerIrq1->getLine("ICF1"),
189  inputCapture1);
190 
191  timerIrq2 = new TimerIRQRegister(this, irqSystem, 2);
192  timerIrq2->registerLine(0, IRQLine("TOV2", 11));
193  timerIrq2->registerLine(1, IRQLine("OCF2A", 9));
194  timerIrq2->registerLine(2, IRQLine("OCF2B", 10));
195 
196  timer2 = new HWTimer8_2C(this,
197  &premux2,
198  2,
199  timerIrq2->getLine("TOV2"),
200  timerIrq2->getLine("OCF2A"),
201  PinAtPort(&portd, 7),
202  timerIrq2->getLine("OCF2B"),
203  PinAtPort(&portd, 6));
204 
205  gpior0_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR0");
206  gpior1_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR1");
207  gpior2_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR2");
208 
209  admux = new HWAdmuxM16(this, &porta.GetPin(0), &porta.GetPin(1), &porta.GetPin(2),
210  &porta.GetPin(3), &porta.GetPin(4), &porta.GetPin(5),
211  &porta.GetPin(6), &porta.GetPin(7));
212  aref = new HWARef4(this, HWARef4::REFTYPE_BG3);
213  ad = new HWAd(this, HWAd::AD_M164, irqSystem, 24, admux, aref);
214 
215  acomp = new HWAcomp(this, irqSystem, PinAtPort(&portb, 2), PinAtPort(&portb, 3), 23, ad, timer1);
216 
217  spi = new HWSpi(this,
218  irqSystem,
219  PinAtPort(&portb, 5), // MOSI
220  PinAtPort(&portb, 6), // MISO
221  PinAtPort(&portb, 7), // SCK
222  PinAtPort(&portb, 4), // /SS
223  19, // irqvec
224  true);
225 
226  wado = new HWWado(this);
227 
228  usart0 = new HWUsart(this,
229  irqSystem,
230  PinAtPort(&portd, 1), // TXD0
231  PinAtPort(&portd, 0), // RXD0
232  PinAtPort(&portb, 0), // XCK0
233  20, // (21) RX complete vector
234  21, // (22) UDRE vector
235  22); // (23) TX complete vector
236 
237  usart1 = new HWUsart(this,
238  irqSystem,
239  PinAtPort(&portd, 3), // TXD1
240  PinAtPort(&portd, 2), // RXD1
241  PinAtPort(&portd, 4), // XCK1
242  28, // (29) RX complete vector
243  29, // (30) UDRE vector
244  30, // (31) TX complete vector
245  1); // instance_id for tracking in UI
246 
247  // 0xCF - 0xFF reserved
248 
249  rw[0xCE]= & usart1->udr_reg;
250  rw[0xCD]= & usart1->ubrrhi_reg;
251  rw[0xCC]= & usart1->ubrr_reg;
252  // 0xCB reserved
253  rw[0xCA]= & usart1->ucsrc_reg;
254  rw[0xC9]= & usart1->ucsrb_reg;
255  rw[0xC8]= & usart1->ucsra_reg;
256  // 0xC7 reserved
257  rw[0xC6]= & usart0->udr_reg;
258  rw[0xC5]= & usart0->ubrrhi_reg;
259  rw[0xC4]= & usart0->ubrr_reg;
260  // 0xC3 reserved
261  rw[0xC2]= & usart0->ucsrc_reg;
262  rw[0xC1]= & usart0->ucsrb_reg;
263  rw[0xC0]= & usart0->ucsra_reg;
264  // 0xBF reserved
265  // 0xBE reserved
272  // 0xB7 reserved
273  rw[0xb6]= & assr_reg;
274  // 0xb5 reserved
275  rw[0xb4]= & timer2->ocrb_reg;
276  rw[0xb3]= & timer2->ocra_reg;
277  rw[0xb2]= & timer2->tcnt_reg;
278  rw[0xb1]= & timer2->tccrb_reg;
279  rw[0xb0]= & timer2->tccra_reg;
280  // 0x8c - 0xaf reserved
281  rw[0x8b]= & timer1->ocrb_h_reg;
282  rw[0x8a]= & timer1->ocrb_l_reg;
283  rw[0x89]= & timer1->ocra_h_reg;
284  rw[0x88]= & timer1->ocra_l_reg;
285  rw[0x87]= & timer1->icr_h_reg;
286  rw[0x86]= & timer1->icr_l_reg;
287  rw[0x85]= & timer1->tcnt_h_reg;
288  rw[0x84]= & timer1->tcnt_l_reg;
289  // 0x83 reserved
290  rw[0x82]= & timer1->tccrc_reg;
291  rw[0x81]= & timer1->tccrb_reg;
292  rw[0x80]= & timer1->tccra_reg;
295  // 0x7D reserved
296  rw[0x7C]= & ad->admux_reg;
297  rw[0x7B]= & ad->adcsrb_reg;
298  rw[0x7A]= & ad->adcsra_reg;
299  rw[0x79]= & ad->adch_reg;
300  rw[0x78]= & ad->adcl_reg;
301  // 0x74, 0x75, 0x76, 0x77 reserved
302  rw[0x73]= pcmsk3_reg;
303  // 0x72 reserved
304  // 0x71 reserved
305  rw[0x70]= & timerIrq2->timsk_reg;
306  rw[0x6F]= & timerIrq1->timsk_reg;
307  rw[0x6E]= & timerIrq0->timsk_reg;
308  rw[0x6d]= pcmsk2_reg;
309  rw[0x6c]= pcmsk1_reg;
310  rw[0x6b]= pcmsk0_reg;
311  // 0x6A reserved
312  rw[0x69]= eicra_reg;
313  rw[0x68]= pcicr_reg;
314  // 0x67 reserved
315  rw[0x66]= osccal_reg;
316  // 0x65 reserved
318  // 0x63 reserved
319  // 0x62 reserved
320  rw[0x61]= clkpr_reg;
322  rw[0x5f]= statusRegister;
323  rw[0x5e]= & ((HWStackSram *)stack)->sph_reg;
324  rw[0x5d]= & ((HWStackSram *)stack)->spl_reg;
325  // 0x5c reserved
326  rw[0x5b]= & rampz->ext_reg;
327  // 0x58 - 0x5a reserved
328  rw[0x57]= & spmRegister->spmcr_reg;
329  // 0x56 reserved
333  // 0x52 reserved
335  rw[0x50]= & acomp->acsr_reg;
336  // 0x4F reserved
337  rw[0x4E]= & spi->spdr_reg;
338  rw[0x4D]= & spi->spsr_reg;
339  rw[0x4C]= & spi->spcr_reg;
340  rw[0x4B]= gpior2_reg;
341  rw[0x4A]= gpior1_reg;
342  // 0x49 reserved
343  rw[0x48]= & timer0->ocrb_reg;
344  rw[0x47]= & timer0->ocra_reg;
345  rw[0x46]= & timer0->tcnt_reg;
346  rw[0x45]= & timer0->tccrb_reg;
347  rw[0x44]= & timer0->tccra_reg;
348  rw[0x43]= & gtccr_reg;
349  rw[0x42]= & eeprom->eearh_reg;
350  rw[0x41]= & eeprom->eearl_reg;
351  rw[0x40]= & eeprom->eedr_reg;
352  rw[0x3F]= & eeprom->eecr_reg;
353  rw[0x3E]= gpior0_reg;
354  rw[0x3D]= eimsk_reg;
355  rw[0x3C]= eifr_reg;
356  rw[0x3b]= pcifr_reg;
357  // 0x38, 0x39, 0x3A reserved
358  rw[0x37]= & timerIrq2->tifr_reg;
359  rw[0x36]= & timerIrq1->tifr_reg;
360  rw[0x35]= & timerIrq0->tifr_reg;
361  // 0x2C - 0x34 reserved
362  rw[0x2B]= & portd.port_reg;
363  rw[0x2A]= & portd.ddr_reg;
364  rw[0x29]= & portd.pin_reg;
365  rw[0x28]= & portc.port_reg;
366  rw[0x27]= & portc.ddr_reg;
367  rw[0x26]= & portc.pin_reg;
368  rw[0x25]= & portb.port_reg;
369  rw[0x24]= & portb.ddr_reg;
370  rw[0x23]= & portb.pin_reg;
371  rw[0x22]= & porta.port_reg;
372  rw[0x21]= & porta.ddr_reg;
373  rw[0x20]= & porta.pin_reg;
374 
375  Reset();
376 }
377 
IOSpecialReg * pcifr_reg
PCIFR IO register.
ADC reference is selected on 3 or 4 different sources: Vcc, aref pin, bandgap or 2.56V reference.
Definition: hwad.h:60
Basic AVR device, contains the core functionality.
Definition: avrdevice.h:66
0:aref, 1:vcc, 2:bg, 3:2.56V
Definition: hwad.h:68
PrescalerMultiplexerExt premux0
prescaler multiplexer for timer 0
IOSpecialReg * eicra_reg
EICRA IO register.
AvrFuses * fuses
Definition: avrdevice.h:100
AddressExtensionRegister * rampz
RAMPZ address extension register.
Definition: avrdevice.h:105
HWIrqSystem * irqSystem
Definition: avrdevice.h:104
ICaptureSource * inputCapture1
input capture source for timer1
HWAcomp * acomp
analog compare unit
ExternalIRQHandler * extirqpc
external interrupt support for PCINT[0-2]
IOReg< HWAd > admux_reg
Definition: hwad.h:269
Implements a stack with stack register using RAM as stackarea.
Definition: hwstack.h:131
OSCCALRegister * osccal_reg
OSCCAL IO register.
IOReg< HWUart > ubrrhi_reg
IO register "UBRRxH" - baudrate.
Definition: hwuart.h:136
HWTimer16_2C3 * timer1
timer 1 unit
IOReg< HWEeprom > eedr_reg
Definition: hweeprom.h:101
void registerIrq(int vector, int irqBit, ExternalIRQ *extirq)
Definition: externalirq.cpp:53
IOReg< HWTimer16 > ocra_h_reg
output compare A register, high byte
Definition: hwtimer.h:312
Implement CLKPR register.
Definition: rwmem.h:135
TimerIRQRegister * timerIrq1
timer interrupt unit for timer 1
Pin & GetPin(unsigned char pinNo)
returns a pin reference of pin with pin number
Definition: hwport.cpp:87
oscillator version 5.x, 8bit, two ranges
Definition: rwmem.h:181
IOReg< HWTimer16 > ocra_l_reg
output compare A register, low byte
Definition: hwtimer.h:313
IOReg< HWAcomp > acsr_reg
ACSR IO register.
Definition: hwacomp.h:82
IOReg< HWTimer8 > tcnt_reg
counter register
Definition: hwtimer.h:229
IOSpecialReg * pcmsk1_reg
PCIMSK1 IO register.
Definition: hwwado.h:38
IOSpecialReg * pcmsk3_reg
PCIMSK3 IO register.
HWARef * aref
adc reference unit
A register in IO register space unrelated to any peripheral. "GPIORx" in datasheets.
Definition: rwmem.h:113
IOReg< HWTimer16 > tcnt_h_reg
counter register, high byte
Definition: hwtimer.h:310
IOSpecialReg * eimsk_reg
EIMSK IO register.
GPIORegister * gpior1_reg
general purpose IO register
Handler for external IRQ&#39;s to communicate with IRQ system and mask/flag registers.
Definition: externalirq.h:41
Represents a timer interrupt line, Frontend for timer interrupts.
Definition: timerirq.h:42
void SetFuseConfiguration(int size, unsigned long defvalue)
Configure fuses.
Definition: flashprog.cpp:246
IOReg< AddressExtensionRegister > ext_reg
Definition: ioregs.h:45
IOReg< HWUart > ubrr_reg
IO register "UBRRxL" - baudrate.
Definition: hwuart.h:136
IOReg< HWTimer16_2C3 > tccra_reg
control register A
Definition: hwtimer.h:615
IOReg< HWTimer8_2C > tccrb_reg
control register B
Definition: hwtimer.h:440
IOSpecialReg tifr_reg
the TIFRx register
Definition: timerirq.h:74
IOReg< HWAd > adcsrb_reg
Definition: hwad.h:269
IOReg< HWSpi > spdr_reg
Definition: hwspi.h:121
Implements the I/O hardware necessary to do USART transfers.
Definition: hwuart.h:149
IOReg< HWTimer16_2C3 > tccrb_reg
control register B
Definition: hwtimer.h:616
IOReg< HWPort > port_reg
Definition: hwport.h:84
IOReg< HWUart > ucsra_reg
Definition: hwuart.h:136
void Reset()
Definition: avrdevice.cpp:390
IOReg< HWPort > pin_reg
Definition: hwport.h:84
IOReg< HWTimer8_2C > tccra_reg
control register A
Definition: hwtimer.h:439
GPIORegister * gpior2_reg
general purpose IO register
IOReg< HWTimer16 > icr_h_reg
input capture register, high byte
Definition: hwtimer.h:318
IOReg< HWSpi > spcr_reg
Definition: hwspi.h:121
Timer unit with 16Bit counter and 2 output compare units, but 3 config registers. ...
Definition: hwtimer.h:593
AvrDevice_atmega1284Abase(unsigned ram_bytes, unsigned flash_bytes, unsigned ee_bytes, unsigned nrww_start)
TraceValueCoreRegister coreTraceGroup
Definition: avrdevice.h:108
IOReg< HWUart > ucsrb_reg
Definition: hwuart.h:136
IOReg< HWTimer16 > icr_l_reg
input capture register, low byte
Definition: hwtimer.h:319
IOReg< HWAd > adcsra_reg
Definition: hwad.h:269
IOSpecialReg * pcicr_reg
PCICR IO register.
IOReg< HWEeprom > eearh_reg
Definition: hweeprom.h:101
IOReg< HWTimer16 > tcnt_l_reg
counter register, low byte
Definition: hwtimer.h:311
TimerIRQRegister * timerIrq2
timer interrupt unit for timer 2
HWAdmux * admux
adc multiplexer unit
PrescalerMultiplexer premux2
prescaler multiplexer for timer 2
Pin * GetPin(const char *name)
Definition: avrdevice.cpp:76
IOReg< HWTimer16 > ocrb_l_reg
output compare B register, low byte
Definition: hwtimer.h:315
TimerIRQRegister * timerIrq0
timer interrupt unit for timer 0
HWUsart * usart0
usart 0 unit
Provices flag and mask register for timer interrupts and connects irq lines to irqsystem.
Definition: timerirq.h:61
ADC type M164: ADC on atmega164/324/644/1284 and at90can32/64/128.
Definition: hwad.h:264
IOReg< HWEeprom > eecr_reg
Definition: hweeprom.h:101
HWEeprom * eeprom
Definition: avrdevice.h:102
IOSpecialReg gtccr_reg
GTCCR IO register.
Definition: hwspi.h:38
void registerLine(int idx, IRQLine *irq)
Definition: timerirq.cpp:88
#define AVR_REGISTER(name, class)
Definition: avrfactory.h:69
RWMemoryMember ** rw
The whole memory: R0-R31, IO, Internal RAM.
Definition: avrdevice.h:129
IOSpecialReg * pcmsk0_reg
PCIMSK0 IO register.
Provides the programming engine for flash self programming.
Definition: flashprog.h:38
void SetBootloaderConfig(unsigned addr, int size, int bPosBOOTSZ, int bPosBOOTRST)
Set bootloader support configuration.
Definition: flashprog.cpp:274
IOReg< HWAd > adch_reg
Definition: hwad.h:269
IOReg< HWTimer16 > ocrb_h_reg
output compare B register, high byte
Definition: hwtimer.h:314
HWTimer8_2C * timer0
timer 0 unit
IOReg< HWTimer16_2C3 > tccrc_reg
control register C
Definition: hwtimer.h:617
CLKPRRegister * clkpr_reg
CLKPR IO register.
IOReg< HWSpi > spsr_reg
Definition: hwspi.h:121
IOReg< HWEeprom > eearl_reg
Definition: hweeprom.h:101
IOReg< HWAd > adcl_reg
Definition: hwad.h:269
IOReg< HWTimer8 > ocra_reg
output compare A register
Definition: hwtimer.h:230
static NotSimulatedRegister * getRegister(int reg)
Definition: rwmem.cpp:297
HWStack * stack
Definition: avrdevice.h:131
Class, which provides input capture source for 16bit timers.
Definition: icapturesrc.h:34
HWUsart * usart1
usart 1 unit
PrescalerMultiplexerExt premux1
prescaler multiplexer for timer 1
RWSreg * statusRegister
the memory interface for status
Definition: avrdevice.h:133
IOReg< HWUart > udr_reg
Definition: hwuart.h:136
Timer unit with 8Bit counter and 2 output compare unit.
Definition: hwtimer.h:416
ExternalIRQHandler * extirq012
external interrupt support for INT0, INT1, INT2
Pin-change interrupt on all pins of a port.
Definition: externalirq.h:137
IRQLine * getLine(const std::string &name)
Definition: timerirq.cpp:109
HWWado * wado
WDT timer.
Definition: avrdevice.h:134
Definition: hwad.h:204
FlashProgramming * spmRegister
Definition: avrdevice.h:99
IOReg< HWTimer8 > ocrb_reg
output compare B register
Definition: hwtimer.h:231
IOReg< HWPort > ddr_reg
Definition: hwport.h:84
HWTimer8_2C * timer2
timer 2 unit
IOSpecialReg * eifr_reg
EIFR IO register.
IOReg< HWUsart > ucsrc_reg
Definition: hwuart.h:173
GPIORegister * gpior0_reg
general purpose IO register
IOSpecialReg timsk_reg
the TIMSKx register
Definition: timerirq.h:73
IOSpecialReg assr_reg
ASSR IO register.
Analog comparator peripheral.
Definition: hwacomp.h:42
IOReg< FlashProgramming > spmcr_reg
Definition: flashprog.h:95
Implement OSCCAL register.
Definition: rwmem.h:174
IOSpecialReg * pcmsk2_reg
PCIMSK2 IO register.
External interrupt (INT0, INT1...) on a single pin, one and 2 bit configuration.
Definition: externalirq.h:110
bool flagELPMInstructions
ELPM instructions are available (only on devices with bigger flash)
Definition: avrdevice.h:120