simulavr  1.1.0
hwuart.cpp
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1 /*
2  ****************************************************************************
3  *
4  * simulavr - A simulator for the Atmel AVR family of microcontrollers.
5  * Copyright (C) 2001, 2002, 2003 Klaus Rudolph
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  ****************************************************************************
22  *
23  * $Id$
24  */
25 
26 #include "hwuart.h"
27 #include "helper.h"
28 
29 //usr & ucsra
30 #define RXC 0x80
31 #define TXC 0x40
32 #define UDRE 0x20
33 #define FE 0x10
34 #define OR 0x08
35 #define DOR 0x08 //same for usart
36 #define UPE 0x04 //only usart
37 #define U2X 0x02 //only usart
38 #define MPCM 0x01 //only usart
39 
40 
41 //ucr & ucsrb
42 #define RXCIE 0x80
43 #define TXCIE 0x40
44 #define UDRIE 0x20
45 #define RXEN 0x10
46 #define TXEN 0x08
47 #define CHR9 0x04 //same as ucsz2
48 #define UCSZ2 0x04
49 #define RXB8 0x02
50 #define TXB8 0x01
51 
52 //ussrc usart only
53 #define URSEL 0x80
54 #define UMSEL 0x40
55 #define UPM1 0x20
56 #define UPM0 0x10
57 #define USBS 0x08
58 #define UCSZ1 0x04
59 #define UCSZ0 0x02
60 #define UCPOL 0x01
61 
62 void HWUart::SetUdr(unsigned char val) {
63  udrWrite=val;
64  if ( usr&UDRE) { //the data register was empty
65  usr &=0xff-UDRE; //so we are not able to send another value now
66  if (ucr & UDRIE) { // UDRE irq was allready set, so clear it
68  }
69  }
70 
71 }
72 
73 void HWUart::SetUsr(unsigned char val) {
74  unsigned char usrold=usr;
75  usr = val;
76 
77  unsigned char irqold= ucr & usrold;
78  unsigned char irqnew= ucr & usr;
79 
80  if ( usr & TXC) {
81  usr &=0xff-TXC; //clear TXC if 1 written to TXC
82  }
83 
84  unsigned char changed=irqold^irqnew;
85  unsigned char setnew= changed&irqnew;
86  unsigned char clearnew= changed& (~irqnew);
87 
88  CheckForNewSetIrq(setnew);
89  CheckForNewClearIrq(clearnew);
90 }
91 
92 void HWUart::SetUbrr(unsigned char val) {
93  ubrr = (ubrr & 0xff00) | val;
94 }
95 
96 void HWUart::SetUbrrhi(unsigned char val) {
97  ubrr = (ubrr & 0xff) | ((val & 0xf) << 8);
98 }
99 
101  if ( ucr&UCSZ2) {
102  frameLength=9;
103  } else {
104  switch (ucsrc & (UCSZ1|UCSZ0) ) {
105  case 0:
106  frameLength=5;
107  break;
108 
109  case UCSZ0:
110  frameLength=6;
111  break;
112 
113  case UCSZ1:
114  frameLength=7;
115  break;
116 
117  case UCSZ0|UCSZ1:
118  frameLength=8;
119  break;
120  }
121  }
122 
123  frameLength--; // all compares run from 0..frameLength -> -1
124 }
125 
126 void HWUart::SetUcr(unsigned char val) {
127  unsigned char ucrold=ucr;
128  ucr=val;
130 
131  if (ucr & TXEN) {
133  pinTx.SetAlternatePort(1); //send high bit
134  }
135  pinTx.SetAlternateDdr(1); //output!
138  } else {
141  }
142 
143  if (ucr & RXEN) {
145  pinRx.SetAlternateDdr(0); // input
146  }
147 
148  //prepared for later remove from hwuart from every cpu cycle (only on demand)
149 #if 0
150  //Check if one of Rx or Tx is enabled NEW!
151  if ( ucr & ( RXEN|TXEN) ) {//now one of rx or tx is on
152  if ( !(ucrold & (RXEN|TXEN)) ) { //but there was nothing on before
153  core->AddToCycleList(this); //enable the cpu cycle list!
154  }
155  }
156 #endif
157 
158  unsigned char irqold= ucrold&usr;
159  unsigned char irqnew= ucr&usr;
160 
161 
162  unsigned char changed=irqold^irqnew;
163  unsigned char setnew= changed&irqnew;
164  unsigned char clearnew= changed& (~irqnew);
165 
166  CheckForNewSetIrq(setnew);
167  CheckForNewClearIrq(clearnew);
168 }
169 
170 unsigned int HWUart::CpuCycle() {
171  baudCnt++; // TODO: this isn't implemented right, baud clock prescaler is a down counter!
172  if(baudCnt >= (ubrr + 1)) {
173  baudCnt = 0;
174  CpuCycleRx();
175  CpuCycleTx();
176  }
177 
178  // controling read sequence down counter
179  if(regSeq > 0)
180  regSeq--;
181 
182  return 0;
183 }
184 
185 unsigned int HWUart::CpuCycleRx() {
186  // receiver part
187  //
188  //this part MUST! ONLY BE CALLED IF THE PRESCALER OUTPUT COUNTS
189  if ( ucr & RXEN) {
190  // will be used to cause interrupts (in the end of this if)
191  unsigned char usr_old=usr;
192 
193  switch (rxState) {
194  case RX_WAIT_FOR_HIGH: //wait for startbit
196 
197  break;
198 
199  case RX_WAIT_FOR_LOWEDGE:
201  cntRxSamples=0;
202  rxLowCnt=0;
203  rxHighCnt=0;
204  break;
205 
206  case RX_READ_STARTBIT:
207  cntRxSamples++;
208  if (cntRxSamples>=8 && cntRxSamples<=10) {
209  if (pinRx==0) {
210  rxLowCnt++;
211  } else {
212  rxHighCnt++;
213  }
214  }
215  if (cntRxSamples>15) {
216  if ( rxLowCnt>rxHighCnt) { //yes the startbit is low
217  cntRxSamples=0;
219  rxDataTmp=0;
220  rxLowCnt=0;
221  rxHighCnt=0;
222  rxBitCnt=0;
223  } else {
225  }
226  }
227  break;
228 
229  case RX_READ_DATABIT:
230  cntRxSamples++;
231  if (cntRxSamples>=8 && cntRxSamples<=10) {
232  if (pinRx==0) {
233  rxLowCnt++;
234  } else {
235  rxHighCnt++;
236  }
237  }
238 
239  if (cntRxSamples>15) {
240  if ( rxLowCnt<rxHighCnt) { //the bit was high
241  rxDataTmp|=(1<<rxBitCnt);
242  readParity^=1;
243  }
244 
245  rxBitCnt++;
246  cntRxSamples=0;
247  rxLowCnt=0;
248  rxHighCnt=0;
249 
250  if (rxBitCnt>frameLength) {
251  if (ucsrc&UPM1) {
253  } else {
255  }
256  }
257 
258  }
259 
260  break;
261 
262  case RX_READ_PARITY:
263  cntRxSamples++;
264  if (cntRxSamples>=8 && cntRxSamples<=10) {
265  if (pinRx==0) {
266  rxLowCnt++;
267  } else {
268  rxHighCnt++;
269  }
270  }
271 
272  if (cntRxSamples>15) {
273  bool actParity;
274 
275  if ( rxLowCnt<rxHighCnt) { //the bit was high
276  actParity=1;
277  } else {
278  actParity=0;
279  }
280 
281  if (ucsrc & UPM0) { //odd parity
282  actParity=!actParity;
283  }
284 
285  if (readParity==actParity) {
286  usr&=0xff-UPE; //clear parity error
287  } else {
288  usr|=UPE;
289  }
290  }
291  break;
292 
293 
294 
295  case RX_READ_STOPBIT:
296  cntRxSamples++;
297  if (cntRxSamples>=8 && cntRxSamples<=10) {
298  if (pinRx==0) {
299  rxLowCnt++;
300  } else {
301  rxHighCnt++;
302  }
303  }
304 
305  if (
306  ((ucsrc&USBS) && (cntRxSamples>16)) || //if 2 stopbits used we have to wait full bit frame
307  ((!(ucsrc&USBS)) && (cntRxSamples>10)) //in case of only 1 stopbit we can shorten the stopbit
308  ) {
309 
310  if ( rxLowCnt<rxHighCnt) { //the bit was high this is ok
311  udrRead=rxDataTmp&0xff;
312  usr&=0xff-FE;
313  if ( (ucr & CHR9) !=0 ) {
314  if ( rxDataTmp&0x100) {
315  ucr|=RXB8;
316  } else {
317  ucr&=0xff-RXB8;
318  }
319 
320  }
321  } else { //stopbit was low so set framing error
322  udrRead=rxDataTmp&0xff;
323  usr|=FE;
324  }
325  if (ucsrc&USBS) {
326  cntRxSamples=0;
327  rxLowCnt=0;
328  rxHighCnt=0;
330  } else {
331  if (usr&RXC) { //RXC is allready set->Overrun Error
332  usr|=OR;
333  }
334  usr|=RXC; //receiving is complete, regardless of framing error!
335  if (rxLowCnt<rxHighCnt)
337  else
339  }
340  }
341  break;
342 
343  case RX_READ_STOPBIT2:
344  cntRxSamples++;
345  if (cntRxSamples>=8 && cntRxSamples<=10) {
346  if (pinRx==0) {
347  rxLowCnt++;
348  } else {
349  rxHighCnt++;
350  }
351  } else if (cntRxSamples>10) { //the last stopbit could allways be shorter than normal data-bit
352  if ( rxLowCnt<rxHighCnt) { //the bit was high this is ok
353  usr&=0xff-FE;
354  } else { //stopbit was low so set framing error
355  usr|=FE;
356  }
357 
358  usr|=RXC; //receiving is complete, regardless of framing error!
359  if (rxLowCnt<rxHighCnt)
361  else
363  }
364  break;
365 
366  case RX_DISABLED:
367  break;
368  } //end of switch
369 
370  // check if as a result of this operation any interrupt flags sholud be changed.
371  unsigned char irqold= ucr&usr_old;
372  unsigned char irqnew= ucr&usr;
373 
374 
375  unsigned char changed=irqold^irqnew;
376  unsigned char setnew= changed&irqnew;
377  unsigned char clearnew= changed& (~irqnew);
378 
379  CheckForNewSetIrq(setnew);
380  CheckForNewClearIrq(clearnew);
381 
382  } // end of rx enabled
383  return 0;
384 }
385 
386 unsigned int HWUart::CpuCycleTx() {
387  /*************************************** TRANCEIVER PART **********************************/
388  //unsigned char usr_old=usr;
389 
390  baudCnt16++;
391  if(baudCnt16 >= 16) { // TODO: this isn't implemented right, baud clock prescaler is a down counter!
392  baudCnt16 = 0;
393 
394  if (ucr & TXEN ) { //transmitter enabled
395 
396  // will be used to cause interrupts int the end of this if
397  unsigned char usr_old=usr;
398 
399  if (!(usr & UDRE) ) { // there is new data in udr
400  if ((usr & TXC)| (txState==TX_FIRST_RUN)|(txState==TX_FINISH)) { //transmitter is empty
401  //shift data from udr->transmit shift register
403  if (ucr & TXB8) { // there is a 1 in txb8
404  txDataTmp|=0x100; // this is bit 9 in the datastream
405  }
406 
407 
408  usr|=UDRE; // set UDRE, UDR is empty now
409  usr&=0xff-TXC; // the transmitter is not ready
411  } // end of transmitter empty
412  } // end of new data in udr
413 
414  switch (txState) {
415  case TX_SEND_STARTBIT:
418  txBitCnt=0;
419  break;
420 
421  case TX_SEND_DATABIT:
424  txBitCnt++;
425 
426  if (txBitCnt>frameLength) {
427  if (ucsrc & (UPM0|UPM1) ) {
429  } else {
431  }
432  }
433 
434  break;
435 
436  case TX_SEND_PARITY:
437  if( ucsrc & UPM0) {
438  //even parity to send
440  } else {
441  //odd parity to send
443  }
445  break;
446 
447 
448  case TX_SEND_STOPBIT:
450 
451  if (ucsrc & USBS) { //two stop bits needed?
453  } else {
454  //check for new data
455  if (!(usr & UDRE)) { // there is new data in udr
456  //shift data from udr->transmit shift register
458  if (ucr & TXB8) { // there is a 1 in txb8
459  txDataTmp|=0x100; // this is bit 9 in the datastream
460  }
461 
462  usr|=UDRE; // set UDRE, UDR is empty now
464  } // end of new data in udr
465  else
466  {
468  }
469  }
470  break;
471 
472  case TX_SEND_STOPBIT2:
474  //check for new data
475  if (!(usr & UDRE)) { // there is new data in udr
476  //shift data from udr->transmit shift register
478  if (ucr & TXB8) { // there is a 1 in txb8
479  txDataTmp|=0x100; // this is bit 9 in the datastream
480  }
481 
482  usr|=UDRE; // set UDRE, UDR is empty now
484  } // end of new data in udr
485  else
486  {
488  }
489  break;
490 
491  case TX_AFTER_STOPBIT: //transmit complete and no new data
492  usr|=TXC; //set the txc
494  break;
495 
496 
497 
498  case TX_DISABLED:
499  case TX_FIRST_RUN:
500  case TX_FINISH:
501  break;
502 
503  } //end of switch tx state
504 
505  // check if some interrupts should be caused as a result
506  // of this sending tact
507  unsigned char irqold= ucr&usr_old;
508  unsigned char irqnew= ucr&usr;
509 
510 
511  unsigned char changed=irqold^irqnew;
512  unsigned char setnew= changed&irqnew;
513  unsigned char clearnew= changed& (~irqnew);
514 
515  CheckForNewSetIrq(setnew);
516  CheckForNewClearIrq(clearnew);
517 
518  } // end of tx enabled
519  } //end of 1 time baudrate
520 
521 
522  return 0;
523 }
524 
526  HWIrqSystem *s,
527  PinAtPort tx,
528  PinAtPort rx,
529  unsigned int rx_interrupt,
530  unsigned int udre_interrupt,
531  unsigned int tx_interrupt,
532  int instance_id):
533  Hardware(core),
534  TraceValueRegister(core, "UART" + int2str(instance_id)),
535  irqSystem(s),
536  pinTx(tx),
537  pinRx(rx),
538  vectorRx(rx_interrupt),
539  vectorUdre(udre_interrupt),
540  vectorTx(tx_interrupt),
541  udr_reg(this, "UDR",
542  this, &HWUart::GetUdr, &HWUart::SetUdr),
543  usr_reg(this, "USR",
544  this, &HWUart::GetUsr, &HWUart::SetUsr),
545  ucr_reg(this, "UCR",
546  this, &HWUart::GetUcr, &HWUart::SetUcr),
547  ucsra_reg(this, "UCSRA",
548  this, &HWUart::GetUsr, &HWUart::SetUsr),
549  ucsrb_reg(this, "UCSRB",
550  this, &HWUart::GetUcr, &HWUart::SetUcr),
551  ubrr_reg(this, "UBRR",
552  this, &HWUart::GetUbrr, &HWUart::SetUbrr),
553  ubrrhi_reg(this, "UBRRHI",
554  this, &HWUart::GetUbrrhi, &HWUart::SetUbrrhi)
555 {
559 
560  core->AddToCycleList(this);
561 
562  trace_direct(this, "UDR_write", &udrWrite);
563  trace_direct(this, "UDR_read", &udrRead);
564  trace_direct(this, "sUSR", &usr);
565  trace_direct(this, "sUCR", &ucr);
566  trace_direct(this, "sUBR", &ubrr);
567 
568  Reset();
569 }
570 
571 unsigned char HWUart::GetUdr() {
572  if (usr&RXC) {
573  usr&=0xff-RXC; // unset RXC register
574  if (ucr & RXC) {
575  irqSystem->ClearIrqFlag(vectorRx); // and clear interrupt flag
576  }
577  }
578  return udrRead;
579 }
580 
581 unsigned char HWUart::GetUsr() { return usr; }
582 unsigned char HWUart::GetUcr() { return ucr; }
583 unsigned char HWUart::GetUbrr() { return ubrr&0xff; }
584 unsigned char HWUart::GetUbrrhi() { return (ubrr&0xff00)>>8; }
585 
586 void HWUart::ClearIrqFlag(unsigned int vector){
587  //other Uart IRQ Flags can't be cleared by executing the vector here
588  if (vector == vectorTx) {
589  usr&=0xff-TXC;
591  }
592 }
593 
594 void HWUart::CheckForNewSetIrq(unsigned char val) {
595  if (val & RXC) { irqSystem->SetIrqFlag(this, vectorRx); }
596  if (val & UDRE) { irqSystem->SetIrqFlag(this, vectorUdre); }
597  if (val & TXC) { irqSystem->SetIrqFlag(this, vectorTx); }
598 }
599 
600 void HWUart::CheckForNewClearIrq(unsigned char val) {
601  if (val & RXC) { irqSystem->ClearIrqFlag(vectorRx); }
602  if (val & UDRE) { irqSystem->ClearIrqFlag(vectorUdre); }
603  if (val & TXC) { irqSystem->ClearIrqFlag(vectorTx); }
604 }
605 
607  udrWrite = 0;
608  udrRead = 0;
609  usr = UDRE; //UDRE in USR is set 1 on reset
610  ucr = 0;
611  ucsrc = UCSZ1 | UCSZ0;
612  ubrr = 0;
613  baudCnt = 0;
614  baudCnt16 = 0;
615 
616  regSeq = 0;
617 
620 
622 }
623 
624 // implementation of HWUsart
625 
626 void HWUsart::SetUcsrc(unsigned char val) {
627  ucsrc=val;
629 }
630 
631 void HWUsart::SetUcsrcUbrrh(unsigned char val) {
632  if((val & URSEL) == URSEL) {
633  SetUcsrc(val & 0x7f);
634  } else {
635  SetUbrrhi(val);
636  }
637 }
638 
639 unsigned char HWUsart::GetUcsrc() { return ucsrc; }
640 
641 unsigned char HWUsart::GetUcsrcUbrrh() {
642  if(regSeq == 0) {
643  regSeq = 2;
644  return GetUbrrhi();
645  } else {
646  regSeq = 0;
647  return GetUcsrc();
648  }
649 }
650 
652  HWIrqSystem *s,
653  PinAtPort tx,
654  PinAtPort rx,
655  PinAtPort xck,
656  unsigned int vrx,
657  unsigned int vudre,
658  unsigned int vtx,
659  int instance_id,
660  bool mxReg):
661  HWUart(core, s, tx, rx, vrx, vudre, vtx, instance_id),
662  pinXck(xck),
663  ucsrc_reg(this, "UCSRC",
664  this, &HWUsart::GetUcsrc, &HWUsart::SetUcsrc),
665  ubrrh_reg(this, "UBRRH",
666  this, &HWUsart::GetUbrrhi, &HWUsart::SetUbrrhi),
667  ucsrc_ubrrh_reg(this, "UCSRC_UBRRH",
668  this, &HWUsart::GetUcsrcUbrrh, &HWUsart::SetUcsrcUbrrh)
669 {
670  if(mxReg) {
673  } else
675 
676  Reset();
677 }
678 
679 // EOF
void Reset()
Definition: hwuart.cpp:606
T_RxState rxState
Definition: hwuart.h:89
Basic AVR device, contains the core functionality.
Definition: avrdevice.h:66
unsigned char usr
USR register value, also used as UCSRA register value.
Definition: hwuart.h:43
IOReg< HWUsart > ubrrh_reg
Definition: hwuart.h:173
int baudCnt
Definition: hwuart.h:64
HWIrqSystem * irqSystem
Connection to interrupt system.
Definition: hwuart.h:53
bool writeParity
The write parity flag for usart.
Definition: hwuart.h:49
unsigned int vectorRx
Interrupt vector ID for receive interrupt.
Definition: hwuart.h:58
void AddToCycleList(Hardware *hw)
Definition: avrdevice.cpp:51
#define UCSZ2
Definition: hwuart.cpp:48
void SetUdr(unsigned char val)
Definition: hwuart.cpp:62
unsigned int vectorUdre
Interrupt vector ID for UDR empty interrupt.
Definition: hwuart.h:59
unsigned int vectorTx
Interrupt vector ID for sent byte interrupt.
Definition: hwuart.h:60
void SetAlternateDdr(bool val)
Definition: pinatport.cpp:75
void SetUseAlternatePort(bool val)
Definition: pinatport.cpp:90
IOReg< HWUart > ubrrhi_reg
IO register "UBRRxH" - baudrate.
Definition: hwuart.h:136
virtual unsigned int CpuCycle()
Definition: hwuart.cpp:170
int cntRxSamples
Definition: hwuart.h:95
bool readParity
The read parity flag for usart.
Definition: hwuart.h:48
int txBitCnt
Definition: hwuart.h:103
void SetUbrr(unsigned char val)
Definition: hwuart.cpp:92
T_TxState txState
Definition: hwuart.h:90
unsigned int rxDataTmp
Definition: hwuart.h:98
unsigned int CpuCycleTx()
Definition: hwuart.cpp:386
void SetUcr(unsigned char val)
Definition: hwuart.cpp:126
#define UCSZ1
Definition: hwuart.cpp:58
unsigned char GetUcr()
Definition: hwuart.cpp:582
IOReg< HWUart > ubrr_reg
IO register "UBRRxL" - baudrate.
Definition: hwuart.h:136
void SetUbrrhi(unsigned char val)
Definition: hwuart.cpp:96
void SetUcsrcUbrrh(unsigned char val)
Definition: hwuart.cpp:631
unsigned char regSeq
Cycle timer for controling read access to UCSRC/UBRRH combined register.
Definition: hwuart.h:62
#define TXC
Definition: hwuart.cpp:31
unsigned char udrWrite
Write stage of UDR register value.
Definition: hwuart.h:41
#define RXB8
Definition: hwuart.cpp:49
Implements the I/O hardware necessary to do USART transfers.
Definition: hwuart.h:149
IOReg< HWUart > ucr_reg
Definition: hwuart.h:136
unsigned char GetUbrr()
Definition: hwuart.cpp:583
IOReg< HWUart > ucsra_reg
Definition: hwuart.h:136
unsigned char GetUcsrcUbrrh()
Definition: hwuart.cpp:641
#define UDRIE
Definition: hwuart.cpp:44
void SetFrameLengthFromRegister()
Definition: hwuart.cpp:100
void SetAlternatePort(bool val)
Definition: pinatport.cpp:85
Build a register for TraceValue&#39;s.
Definition: traceval.h:442
#define UPM0
Definition: hwuart.cpp:56
IOReg< HWUart > usr_reg
Definition: hwuart.h:136
IOReg< HWUart > ucsrb_reg
Definition: hwuart.h:136
void SetIrqFlag(Hardware *, unsigned int vector_index)
Definition: irqsystem.cpp:243
void SetUsr(unsigned char val)
Definition: hwuart.cpp:73
#define UDRE
Definition: hwuart.cpp:32
#define OR
Definition: hwuart.cpp:34
unsigned char txDataTmp
Definition: hwuart.h:102
#define CHR9
Definition: hwuart.cpp:47
HWUart(AvrDevice *core, HWIrqSystem *, PinAtPort tx, PinAtPort rx, unsigned int rx_interrupt, unsigned int udre_interrupt, unsigned int tx_interrupt, int instance_id=0)
Creates a instance of HWUart class.
Definition: hwuart.cpp:525
unsigned char GetUsr()
Definition: hwuart.cpp:581
unsigned char GetUcsrc()
Definition: hwuart.cpp:639
#define USBS
Definition: hwuart.cpp:57
std::string int2str(int i)
Convert an int into a string.
Definition: helper.cpp:59
int rxHighCnt
Definition: hwuart.h:97
void ClearIrqFlag(unsigned int)
Definition: hwuart.cpp:586
#define RXEN
Definition: hwuart.cpp:45
int baudCnt16
Definition: hwuart.h:101
void SetUseAlternateDdr(bool val)
Definition: pinatport.cpp:80
IOReg< HWUsart > ucsrc_ubrrh_reg
Definition: hwuart.h:173
#define UPM1
Definition: hwuart.cpp:55
PinAtPort pinRx
RX pin.
Definition: hwuart.h:56
#define URSEL
Definition: hwuart.cpp:53
void DebugVerifyInterruptVector(unsigned int vector_index, const Hardware *source)
In datasheets RESET vector is index 1 but we use 0! And not a byte address.
Definition: irqsystem.cpp:297
void CheckForNewClearIrq(unsigned char)
Definition: hwuart.cpp:600
unsigned char ucr
UCR register value, also used as UCSRB register value.
Definition: hwuart.h:44
#define TXEN
Definition: hwuart.cpp:46
unsigned char GetUbrrhi()
Definition: hwuart.cpp:584
IOReg< HWUart > udr_reg
Definition: hwuart.h:136
int rxBitCnt
Definition: hwuart.h:99
#define RXC
Definition: hwuart.cpp:30
void ClearIrqFlag(unsigned int vector_index)
Definition: irqsystem.cpp:258
int rxLowCnt
Definition: hwuart.h:96
#define TXB8
Definition: hwuart.cpp:50
int frameLength
Hold length of UART frame.
Definition: hwuart.h:51
PinAtPort pinTx
TX pin.
Definition: hwuart.h:55
Implements the I/O hardware necessary to do UART transfers.
Definition: hwuart.h:38
void CheckForNewSetIrq(unsigned char)
Definition: hwuart.cpp:594
unsigned char GetUdr()
Definition: hwuart.cpp:571
#define FE
Definition: hwuart.cpp:33
#define UPE
Definition: hwuart.cpp:36
unsigned short ubrr
Baud rate register value (UBRR)
Definition: hwuart.h:46
unsigned char ucsrc
UCSRC register value.
Definition: hwuart.h:45
IOReg< HWUsart > ucsrc_reg
Definition: hwuart.h:173
void SetUcsrc(unsigned char val)
Definition: hwuart.cpp:626
#define UCSZ0
Definition: hwuart.cpp:59
unsigned char udrRead
Read stage of UDR register value.
Definition: hwuart.h:42
HWUsart(AvrDevice *core, HWIrqSystem *, PinAtPort tx, PinAtPort rx, PinAtPort xck, unsigned int rx_interrupt, unsigned int udre_interrupt, unsigned int tx_interrupt, int instance_id=0, bool mxReg=true)
Creates a instance of HWUsart class.
Definition: hwuart.cpp:651
TraceValue * trace_direct(TraceValueRegister *t, const std::string &name, const bool *val)
Register a directly traced bool value.
Definition: traceval.cpp:788
unsigned int CpuCycleRx()
Definition: hwuart.cpp:185
void releaseTraceValue(void)
Definition: rwmem.h:320